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march 2011 sensors final data sheet v2.0 tle5011 gmr angle sensor
edition 2011-03 published by infineon technologies ag 81726 munich, germany ? 2011 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
tle5011 final data sheet 3 v2.0, 2011-03 we listen to your comments any information within this doc ument that you feel is wron g, unclear or missing at a ll? your feedback will help us to continously improve the quality of this document. please send your proposal (including a reference to this document) to: sensors@infineon.com revision history: 2011-03, v2.0 previous revision: v1.0 page subjects (major cha nges since last revision) 6 ordering code updated 7 section 1.2 updated 14 table 3, supply voltage and magnet ic induction expanded; figure 7 added 15 table 4; notes of supply current expanded 16 table 5; table 6 added 17 table 7, esd expanded 21 table 10, notes updated 27 table 14, register 0x0d updated 42 package outline in figure 23 modified 43 figure 24 added general spelling and typing errors
tle5011 table of contents final data sheet 4 v2.0, 2011-03 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5.1 internal power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5.2 gmr voltage regulator vrg (vddg-voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 2.5.3 analog voltage regulator vra (vdda-voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5.4 digital voltage regulator vrd (vddd-vol tage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5.5 phase-locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5.6 safety features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.1 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4.3 gmr parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 offset and amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 offset definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 amplitude definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 temperature-dependent behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 orthogonality definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 gmr values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 calibration conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 angle calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6.1 components of the output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6.2 gmr error compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 temperature-dependent offset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 offset correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 amplitude normalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 non-orthogonality correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 resulting angle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6.3 gmr parameters after calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 clock supply (clk timing definition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9 synchronous serial communication interface (ssc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 3.9.1 ssc timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ssc timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table of contents
tle5011 table of contents final data sheet 5 v2.0, 2011-03 3.9.2 ssc baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.9.3 ssc spike filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ssc spike filter off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ssc spike filter on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 filter for data and cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.9.4 ssc data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.9.5 ssc command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 reserved registers (08 h to 0b h ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.9.6 data communication via ssc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.9.7 crc generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.9.8 slave-active byte generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 example1: crc calculation (update x and y and set adc- test mode) . . . . . . . . . . . . . . . . . . . 35 example2: use of two tle5011 units in a bus mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.10 test structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.10.1 functional angle tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 adc test vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.10.2 temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.10.3 functional angle test and temperat ure measurement timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.11 overvoltage comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.11.1 internal supply voltage comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.11.2 v dd overvoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.11.3 gnd-off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.11.4 v dd - off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 package outline pg-dso-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 footprint pg-dso-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
type marking ordering code package tle5011 5011 sp000857850 pg-dso-8 gmr angle sensor tle5011 final data sheet 6 v2.0, 2011-03 1 product description 1.1 overview the tle5011 is a 360 angle sensor that detects the orientation of a magnetic field by measuring sine and cosine angle components with monolithic i ntegrated g iant m agneto r esistance ( igmr ) elements. data communications are accomplished with a bi-directional s ynchronous s erial c ommunication ( ssc ) interface that is spi compatible. the sine and cosine values can be read out digitally. these signals can be digitally processed to calculate the angle orientation of the magnetic field (magnet). this calculat ion can be done by using a co ordinate r otation di gital c omputer ( cordic ) algorithm. it is possible to connect more than one tle5011 to one ssc interface of a microcontroller for redundancy or any other reason. if multiple tle5011 dev ices are used, the synchronization of the connected tle5011 is performed by a broadcast command. each connected tle5011 can be addressed by a dedicated chip select cs pin.
tle5011 product description final data sheet 7 v2.0, 2011-03 1.2 features ? g iant m agneto r esistance (gmr)- based principle ? integrated magnetic field sensing for angle measurement ? designed for 3.3 v and 5 v systems ? full 0 - 360 angle measurement ? highly accurate single-bit sd-adc ? 16-bit representation of sine / c osine values on the interface ? wide magnetic operating range: 30mt to 50mt ? bi-directional ssc interface up to 2 mbit/s ? 3-pin ssc interfac e, spi compatible with open drain ? adcs and filters synchronized wi th external commands via ssc ? test resistors for simulating angle values ? core supply voltage 2.5 v ? 0.25-m cmos technology ? automotive qualified: -40c to +150c (junction temperature) ? latch-up immunity according jedec standard ? esd > 4 kv (hbm) ? green package with lead-free (pb-free) plating 1.3 application example the tle5011 gmr angle sensor is designed for angular po sition sensing in automotive applications, such as: ? steering angle ? brushless dc motor commutation (e.g. e lectric p ower s teering ( eps )) ? rotary switch ? general angular sensing
tle5011 functional description final data sheet 8 v2.0, 2011-03 2 functional description 2.1 general the gmr angle sensor is implemented in vertical inte gration. this means that the gmr active areas are integrated above the logic portion of the tle5011 de vice. gmr elements change their resistance depending on the direction of the magnetic field. four individual gmr elements are connected to one w heatstone sensor bridge. these gmr elements sense either of two components of the applied magnetic field: ? x component, v x (cosine) ? y component, v y (sine) the advantage of a full-bridge structure is that the amplitude of the gmr signal is doubled. figure 1 sensitive bridges of the gmr angle sensor note: in figure 1 , the arrows in the resistor symbols denote the direction of the reference layer, which is used for the further explanation ( figure 2 ). the output signal of each bridge is only unambiguous over 180 between two maxima. therefore two bridges are orientated orthogonally to each other to measure the 360 angle range. using the arctan function, the true 360 angle value can be calculated that is represented by the relation of the cosine (here x) and sine (here y) signals. because only the relative values influence the result, the absolute size of the two signals is of minor importance. therefore, most influences on the amplitudes are compensated. v ddg gnd adc x + gmr resistors adc x -adc y +adc y - v x v y 0 n s 90
tle5011 functional description final data sheet 9 v2.0, 2011-03 figure 2 ideal output of the gmr angle sensor 2.2 pin configuration figure 3 pin configuration (top view) 2.3 pin description table 1 pin describtion pin no. symbol in/out function 1 clk i chip clock 2 sck i ssc clock 3 cs i ssc chip select 4 data i/o ssc data, open drain 5 tst1 i/o test pin 1, must be connected to gnd 6 v dd - supply voltage 7 gnd - ground 8 tst2 i/o test pin 2, must be connected to gnd v angle 90 180 270 360 0 v x (cos) x component (cos) y component (sin) v y (sin) v y v x 12 34 5 6 7 8 center of sensitive area
tle5011 functional description final data sheet 10 v2.0, 2011-03 2.4 block diagram the block diagram shows all switches in the reset position. figure 4 block diagram yh yl xh xl tle5011 ssc control fsm sck data cs differential comb filter fir filter 16 comb filter fir filter fsync fcnt 16 vra vra_ rst vra_ ov vrd_rst vrd_ ov vrd vdd 16 16 pll clk reset analog clock digital clock digital reset vrg_ rst vrd_rst lock vra_ rst tst1 tst 2 1 1 gmr x vddg vddg gnd gnd gmr y angle voltage angle voltage vdd-off comp clk sck vdd_ov comp gnd-off comp vrg vrg_rst vrg _ov gnd temper atur e sensor a d a d 2 2 2 vdd_max tst 1
tle5011 functional description final data sheet 11 v2.0, 2011-03 2.5 functional block description 2.5.1 internal power supply the internal stages of the tle5011 are supplied with different voltage regulators: ? gmr voltage regulator vrg ? analog voltage regulator vra ? digital voltage regulator vrd each voltage regulator has its own overvo ltage and undervoltage detection circuits. 2.5.2 gmr voltage regulat or vrg (vddg -voltage) the gmr voltage regulato r supplies all gmr parts: ?gmr bridges ? test voltages for angle test ? adc reference voltage the voltages are monitored in the vrg overvoltage and undervoltage detectors. 2.5.3 analog voltage regul ator vra (vdda-voltage) the analog voltage regulator supplies the analog parts: ?adcs ? pll (analog) ? vdd-off comparator ? gnd-off comparator ? v dd overvoltage detection the voltages are monitored in the vra overvoltage and undervoltage detectors. 2.5.4 digital voltage regul ator vrd (vddd-voltage) the digital voltage regulator supplies all digital parts: ? comb filters, fir filters ? pll (digital) ? control fsm with bitmap ? ssc interface ? counters (reset, fsync, fcnt) the voltages are monitored in the vrd overvoltage and undervoltage detectors. 2.5.5 phase-locked loop (pll) the clock for the sensors is provided externally. this ensures synchronous operation in case of multiple system participants. the sensor has its own pll to generate the nece ssary clock frequency for the chip operation.
tle5011 functional description final data sheet 12 v2.0, 2011-03 2.5.6 safety features the tle5011 has a multiplicity on safety features to support safety integrity level (sil). sensors meeting this performance standard are identified by infineon with the following logo: figure 5 pro sil logo safety features are: ? angle test (generated via test voltages feeding the adc). ? crossed signal paths (switchable for comparison) ? invertable adc bitstreams ? overvoltage and undervoltage detection of internal and external voltages ?v dd -off and gnd-off to detect supply malfunctions ? frame counter and syn chronisation counter ? separate bandgap-reference voltages for regulators and comparators ? crc-protected ssc protocol ? locked configuration registers disclaimer pro-sil? is a registered tradem ark of infineon technologies ag the pro-sil? trademark designates infineon produ cts which contain sil supporting features. sil supporting features are intended to support the ov erall system design to reach the desired sil (according to iec61508) or a-sil (according to iso26262) le vel for the safety system with high efficiency. sil respectively a-sil certification fo r such a system has to be reached on system level by the system respon- sible at an accredited certification authority. sil stands for safety integrity level (according to iec 61508) a-sil stands for automotive-safety integrity level (according to iso 26262)
tle5011 specification final data sheet 13 v2.0, 2011-03 3 specification 3.1 application circuit the application circuit shows the microcontr oller version with open -drain capabilities. figure 6 application circuit a complete system may consist of one tle5011 and a mi crocontroller. the second tle5011 may be used for redundancy to incr ease system reliability. the mi crocontroller should contain a cordic coprocessor for fast angle calculations, and flash memory for the calibration data storage. 3.2 absolute maximum ratings note: stresses above the ma x. values listed here may cause permane nt damage to the device. exposure to absolute maximum rating conditions for extended period s may affect device reliab ility. maximum ratings are absolute ratings; exceeding only one of these values ma y cause irreversible damage to the integrated circuit. table 2 absolute maximu m rating parameters parameter symbol limit values unit notes min. max. voltage on v dd pin with respect to ground ( v ss ) v dd -0.5 6.5 v max 40 h / lifetime voltage on any pin with respect to ground (v ss ) v in -0.5 6.5 v v dd + 0.5 v may not be exceeded junction temperature t j -40 150 c 150 c for 1000 h not additive magnetic field induction b - |125| mt max 5 min. @ t a =25c - |100| max 5 h @ t a =25c - |70| max 1000 h @ t a =85c not additive - |60| max 1000 h @ t a = 100c not additive storage temperature t st -40 150 c without magnetic field can rx can tx voltage regulator gmr- sensor tle501 1 12v gnd can controller master data_i sc k csq ssc clk 1k each 100 r 100 r 100 nf vd d vd d gnd data_o can tranceiver
tle5011 specification final data sheet 14 v2.0, 2011-03 3.3 operating range to ensure correct operation of the tle5011, the operating conditions identified in table 3 must not be exceeded. all parameters specified in the followi ng sections refer to these operating conditions, unless otherwise indicated. table 3 is valid for -40c < t j < 150c the field strength of a magnet can be selected within the colored area in figure 7 . by limitation of the junction temperature, a higher magnetic field can be applied. in case of a maximum temperature t j = 100c a magnet with up to 60mt at t a = 25c is allowed. figure 7 magnet performance (ambient temperature) table 3 operating range parameter symbol limit values unit notes min. typ. max. supply voltage v dd 3.0 - 5.5 v for 3.3 & 5.0v systems 1) 1) directly blocked with 100-nf ceramic capacitor output current i q --5-10ma 2) 3) 2) maximum current to gnd over open drain output 3) the corresponding voltage levels are listed in table 5 and table 6 input voltage v in -0.3 - 5.5 v v dd + 0.35 v may not be exceeded magnetic induction at t a = 25c 4) 5) 4) values refer to an homogenous magnetic field (b xy ) without vertical magnetic induction (b z = 0mt) 5) see figure 7 b xy 30 - 50 mt -40c < t j <150c b xy 30 - 60 mt -40c < t j <100c b xy 30 - 70 mt -40c < t j <85c expanded magnetic induction at t a = 25c 4) 5) b xy 25 - 30 mt additional angle error of 0.1 6) 6) 0h angle range ang 0 - 360 sine / cosine
tle5011 specification final data sheet 15 v2.0, 2011-03 note: the thermal resistances listed in table 21 ?package parameters? on page 42 must be used to calculate the corresponding ambient temperature. calculation of the junction temperature the total power dissipation p tot of the chip increases its temper ature above the ambient temperature. the power multiplied by the total thermal resistance r thja (junction to ambient) leads to the final junction temperature. r thja is the sum of the addition of th e values of the two components junction to case and case to ambient . r thja = r thjc + r thca t j = t a + t t = r thja xp tot =r thja x( v dd x i dd + v out x i out ) i dd , i out > 0, if direction is into ic example (assuming no load on vout): ? v dd = 5 v ? i dd = 15 ma ? t =150 [k / w] x (5 [v] x 0.015 [a] + 0 [va] ) =11.25 k for moulded sensors, the calculation with r thjc is more adequate. 3.4 characteristics 3.4.1 electrical parameters the indicated electrical parameters apply to the full op erating range, unless otherwise specified. the typical values correspond to a supply voltage v dd = 5.0 v and 25c, unless individually spec ified. all other values correspond to - 40c < t j < 150c. table 4 electrical parameters parameter symbol limit values unit notes min. typ. max. supply current 1) i dd -1520ma v dd = 3.0 to 5.5v --21 v dd =6.5v por level v por 2.0 2.3 2.9 v power-on reset por hysteresis v porhy -30- mv power-on time t pon 50 100 200 s v dd > v ddmin & after first edge on f clk pll jitter t plljit_s -1.32 . 0 2) ns short term 3) t plljit_l 3.0 3.9 long term 4) adc noise 5) n adc - 1 2.2 digits 1 @ fir_byp = 0 -24.4 2) 1 @ fir_byp = 1
tle5011 specification final data sheet 16 v2.0, 2011-03 table 5 electrical parameters for 3.0v < v dd <3.6v table 6 electrical parameters for 4.5v < v dd <5.5v input signal low level v l -0.35 - 0.3 v dd v tested only at data pin as structures of all pins are identical input signal high level v h 0.7 v dd -v dd +0.35 v capacitance of ssc data pin c ldata -46 2) pf internal 1) without external pull-up resistor for ssc interface 2) not subject to production test - ve rified by design/characterization 3) from pulse to pulse 4) accumulated over 1 ms 5) adc noise with respect to t he peak adc value specified in ?signal processing? on page 21 . noise tested using 1 of 100 sample values from angle test ?000? parameter symbol limit values unit notes min. typ. max. input hysteresis v hy3 0.02 v dd -- v pull-up current i pu3 -5 - -50 a cs , data pull-down current i pd3 10 - 150 a sck, clk 8 - 100 tst1 5 - 50 tst2 output signal low level v ol3 - - - - - - 1.3 0.9 0.4 v i q =-10ma i q =-7ma 1) i q =-2.5ma 1) 1) not subject to production test - ve rified by design/characterization parameter symbol limit values unit notes min. typ. max. input hysteresis v hy5 0.07 v dd -- v pull-up current i pu5 -10 - -150 a cs , data pull-down current i pd5 15 - 225 a sck, clk 15 - 225 tst1 10 - 150 tst2 output signal low level v ol5 - - - - 0.7 0.4 v i q =-10ma i q =-5ma 1) 1) not subject to production test - ve rified by design/characterization table 4 electrical parameters parameter symbol limit values unit notes min. typ. max.
tle5011 specification final data sheet 17 v2.0, 2011-03 3.4.2 esd protection 3.4.3 gmr parameters all parameters apply over the full operat ing range, unless othe rwise specified. offset and amplitude figure 8 offset and amplitude definition table 7 esd protection parameter symbol limit values unit notes min. max. esd voltage v hbm - 4kvhbm 1) 1) human body model (hbm) according to: aec-q100-002 v sdm - 500 v sdm 2) 2) socketed device model (sdm) accord ing to: esda/ansi/esd sp5.3.2-2008 table 8 basic gmr parameters parameter symbol limit values unit notes min. typ. max. x, y output range rg adc -- 23230 digits x, y amplitude 1) 1) see figure 2 a x, a y 6000 9500 15781 digits at calibration conditions 3922 - 20620 operating range x, y synchronism 2) 2) k = 100 x (a x /a y ). k 80 100 120 % at calibration conditions x, y offset 3) 3) o sin =(y max +y min )/2; o cos =(x max +x min )/2 o x , o y -3000 0 3000 digits at calibration conditions x, y orthogonality error ? -10.0 0 10.0 at calibration conditions x, y without field x 0 , y 0 -5000 - 5000 digits without magnet 4) 4) not subject to production test - ve rified by design/characterization angle 90 180 270 360 0 +a offset v y 0 -a
tle5011 specification final data sheet 18 v2.0, 2011-03 offset definition the offset of the x and y signals is defined as the mean value between the signed maximum and minimum values of the idealized sine or cosine wave. amplitude definition the amplitude is defined as half the difference between the signed maximum and minimum values of the idealized sine or cosine wave. temperature-dependent behavior the temperature offset gradients for both channels depend on the value at 25c. the gradients can be calculated using the following linear equations: o x25 , o y25 : offset values at 25c in digits. the application note ?tle5011 calibration? describes in chapter 2.3, how to determine the coefficients (kt ox , kt oy ). orthogonality definition the corresponding maximum and zero-crossing points of the sin and cos signals do not occur at the precise distance of 90. the difference between x and y phase is called the orthogonality error . ? ideal = 0 ? x : phase error of x (= cos) signal ? y : phase error of y (= sin) signal o x x max x min + 2 ----------------- ---------------- = o y y max y min + 2 ----------------- --------------- - = a x x max x min ? 2 ---------------- ---------------- - = a y y max y min ? 2 ---------------- ---------------- = kt ox tco_d_x tco_k_x o x25 () + = kt oy tco_d_y tco_k_y o y25 () + = ?? x ? y ? =
tle5011 specification final data sheet 19 v2.0, 2011-03 3.5 calibration gmr values the end-of-line calibration can be accomplished using following sequence: 1. turn magnetic field 360 left and measure x and y values 2. calculate amplitude, offset, phase correction values of left turn 3. turn further 90 left and 90 back right without measurement 4. turn magnetic field 360 right and measure x and y values 5. calculate amplitude, offset, phase correction values of right turn 6. calculate mean values of amplitude, offset, phase correction values the conditions are specified in table 9 . the values obtained from this sequence must be stored in a non-volatile memory. they are used for the correction of the read-out x and y values before the angular calculation. the resulting angular deviation is calcul ated using the parameters determined above. temperature measurement the signal amplitude t 25 of the temperature measurement path at the calibration conditions must be measured and stored. calibration conditions all errors are related to calibration performed by infineon under the following conditions: 3.6 angle calculation 3.6.1 components of the output signals the x and y signals at the output can be described by the following equations: a x : amplitude of x (= cos) signal a y : amplitude of y (= sin) signal o x : offset of x (= cos) signal o y : offset of y (= sin) signal ? x : phase error of x (= cos) signal ? y : phase error of y (= sin) signal 3.6.2 gmr error compensation temperature-dependent offset value to increase the accuracy, the temperature-dependent offs et drift can be compensated. the temperature of the chip must be read out. the offset values o x and o y can be described by the following equations. table 9 gmr test calibration conditions at ifx parameter symbol limit values unit notes min. typ. max. flux density b cal -30- mt b z =0mt temperature t cal -25- c xa x ? x + () cos o x + = ya y ? y + () sin o y + =
tle5011 specification final data sheet 20 v2.0, 2011-03 o x 25 , o y 25 : offset value at 25c in digits t 25 : temperature value at 25c in digits t : temperature value in digits s t : sensitivity of the temperat ure measurement path, (see ?temperature measurement? on page 38 ). offset correction after the x and y values are read out, the temper ature-corrected offset va lue must be subtracted. amplitude normalization next, the x and y values are normalized using the peak values determined in the calibration. non-orthogonality correction the influence of the non-orthogonalit y can be compensated using thefollowing equation, in which only the y channel must be corrected. resulting angle after correction of all errors, the resulting angle can be calculated using the arctan function 1) . 1) microcontroller function ?arctan2(y 3 ,x 2 )? to resolve 360 o x o x25 kt ox s t ------------- - tt 25 ? () + = o y o y25 kt oy s t ------------- - tt 25 ? () + = x 1 xo x ? = y 1 yo y ? = x 2 x 1 a x ------ = y 2 y 1 a y ------ = y 3 y 2 x 2 ? ? () sin ? ? ? () cos --------------- -------------- ------------- - = arc y 3 x 2 ------ ?? ?? tan ? x ? =
tle5011 specification final data sheet 21 v2.0, 2011-03 3.6.3 gmr parameters after calibration after calibration under the conditions specified in table 9 ?gmr test calibratio n conditions at ifx? on page 19 , the sensor has a remaining error as shown in table 10 . the error value refers to b z = 0 mt and operating conditions given in table 3 ?operating range? on page 14 . 3.7 signal processing table 10 gmr parameter with temperature-dependent offset compensation parameter symbol limi t values unit notes min. typ. 1) 1) at 25c, b=30mt max. overall angle error err - 0.7 1.6 including temperature drift 2) 3) 2) including hysteresis error 3) at 0h - - 2.2 including lifetime and temperature drift 2) 4) 4) not subject to production test - ve rified by design/characterization table 11 signal processing parameter symbol limit values unit notes min. typ. 1) 1) for 4-mhhz input frequency max. internal cutoff frequency (-3db) of sin or cos value f cut-off - 4.9 - khz fir_byp=0 19.6 fir_byp=1 update time of sin or cos value 2) 2) t upd = 8192 / (25 x f clk ) for fir_byp = 0 t upd = 8192 / (100 x f clk ) for fir_byp = 1 t upd - 81.9 - s fir_byp=0 - 20.5 - fir_byp=1 settle time 3) 3) t settle =2xt upd , after change of adc input source t settle -163.8- fir_byp=0 - 41.0 - fir_byp=1 peak adc output value adc pk - - 23230 digits signed 16-bit integer (2s complement) 4) 5) 6) 4) output values are valid up to this limit. above it, corrupted results may occur due to non-linearity of the adc. 5) one digit typically represents 5.166 v 6) corresponds to max. gmr output value
tle5011 specification final data sheet 22 v2.0, 2011-03 3.8 clock supply (clk timing definition) the clock signal input ?clk? must fulfill cert ain requirements descri bed in this section: ? the high or low pulse width must not exceed the s pecified values, because the pll needs a minimum pulse width and must be spike filtered. ? the duty-cycle factor should be 0.5 but ca n deviate from the values limited by t clkh(f_min) and t clkl(f_min) . ? the pll is triggered at the positive edge of the clock. if more than 2 edges are missing, a chip reset is generated automatically. figure 9 clk timing definition 3.9 synchronous serial co mmunication in terface (ssc) the 3-pin ssc interface has a bidirectional data line ( open drain), a serial clock signal, and chip select. the ssc interface is designed to communicate with a micr ocontroller with bi-directional ssc interface supporting open drain. other microcontrollers may require an external npn transistor. this allows communication with spi-compatible devices. table 12 clk timing specification parameter symbol limit values unit notes min. typ. max. input frequency f clk 3.8 4.00 4.2 mhz clk duty cycle 1) 1) minimum duty-cycle factor: t clkh(f_min) /t clk(f_min) with t clk(f_min) =1/f clk(f_min) maximum duty-cycle factor: t clkh(f_max) /t clk(f_min) with t clkh(f_max) =t clk(f_min) -t clkl(min) clk duty 30 50 70 % clk rise time t clkr - - 20 ns from v l to v h clk fall time t clkf - - 20 ns from v h to v l pll frequency f pll -100- mhz f clk *25 digital clock f dig -25- mhz(25/4)* f clk digital clock periode t dig - 40 - ns 4/(25* f clk ) t clkh t clkl t clk t v l v h
tle5011 specification final data sheet 23 v2.0, 2011-03 figure 10 ssc half-duplex configuration - microcontroller with open drain figure 11 ssc half-duplex configuration - microcontroller without open drain 3.9.1 ssc timing definition ssc timing diagram figure 12 ssc timing definition ssc inactive time ( cs off ) the ssc inactive time defines the delay before the tle5 011 can be selected again after a transfer. the tle5011 reacts only to one command after an ssc inactive time. th en the ssc interface of the tle5011 is disabled until the next ssc inactive time occurs. data data sck sck tle 501x (ssc slave) c (ssc master) typ. 1k *) optional , e.g . 100 clock generator shift register cs cs *) *) *) *) shift register data mrst mtsr sck sck tle 501x (ssc slave) c (ssc master) typ. 1k *) optional , e.g . 100 clock generator shift register cs cs *) *) *) *) optional shift register sck data t sckp cs v l v h v l v h v l v h t csh t csoff t css t datr t datw t sckh t sckl
tle5011 specification final data sheet 24 v2.0, 2011-03 data write time ( t datw ) during this time, the tle5011 changes the data line, so the data are invalid. the data write time values are defined without a pull-up resistor. pull-up time value ( t pu ) the value in table 13 ?ssc timing specification? on page 24 is estimated at 60 ns. figure 13 ssc interface timing details - worst-case specified timing note: the read window includes the sampling of the data bit. for ssc_filt = 1, the 2- of-3 selection is already considered. only the two last data values need to be equal. for ssc_filt = 0, only one sample point is selected. table 13 ssc timing specification note: timing must be calculated according to table 12 ?clk timing specification? on page 22 parameter symbol limit values unit notes min. typ. max. ssc baud rate f ssc -2.02.1 1) 1) f clk /2, synchronized to f clk if fclk = f clk (max) mbit/s cs setup time t css 3* t dig +10 - - ns cs hold time t csh 5* t dig +10 - - ns cs off t csoff 10* t dig -- ns ssc inactive time sck high t sckh 5* t dig -- ns sck low t sckl 5* t dig -- ns data read time (data valid time) t datr 6* t dig -10 - 7* t dig +10 ns ssc_filt = 0 5* t dig -10 - 7* t dig +10 ssc_filt = 1 data write time (data valid time) 2) 2) t pu is the time generated by the pull-up resistor t datw 6* t dig +25 - 7* t dig +50 + t pu ns data slope t dats -2030 3) 3) not subject to production test - ve rified by design/characterization ns falling edge 4) 4) internal slope control of falling edge for data bit transition from v h to v l . sck ssc_filt=0 sck ssc_filt=1 wr t dat w mi n t dat w max t pu wr t dat w mi n t datw max t pu earliest sample timepoint rd t dat r mi n t dat r max rd t datr mi n t datr max earliest sample timepoint of second sample from 2 of 3 filter t sckh t sckl min
tle5011 specification final data sheet 25 v2.0, 2011-03 the margin time shown in table 14 is the time between write access to the ssc data line and the earliest possible sample read of the tle5011 itself for read-back. it is useful to have a maximum di stance between the write and subsequent read. this ensures a reliable read- back of the written data for the slave-active byte generation. 3.9.2 ssc baud rate the ssc baud rate depends on the internal clock frequency. twelve internal digital clock cycles are necessary to en sure reliable operation. therefore, the maximum ssc baud rate depends on the external clk. 3.9.3 ssc spike filter a spike filter for all ssc lin es can be selected via the ssc_filt bit. ssc spike filter off when the spike filter is disabled, each slope with rising voltage is used to define a bit. this is independent of the length of the sampled pulse. fo r example, a positive spike generates a ri sing and a falling edge. ssc spike filter on a sliding window with four consec utive sample bits is analyzed. the sample frequency is: rising edge detect for sck ? after a rising edge (lh combination), at least one of the two following samples must be high. valid bit combinations: 01 11 , 01 10 , 01 01 . ? a falling condition must be detected previously. falling edge detect for sck ? after a falling edge (hl combin ation), at least one of the tw o following samples must be low. valid bit combinations: 10 00 , 10 01 , 10 10 . ? a rising condition must be detected previously. table 14 maximum pull-up time margin with worst-case specified timing ssc_filt ssc_timing min. t pu margin 1) 1) calculation: margin=t sckl(min) +t datwmax -(t pu )-t datrmin .for margin<50 ns no problems can occur. unit comment 0 don?t care 90 ns 150 f ssc f clk 2 ---------- - = f s 1 f digit -------------- - =
tle5011 specification final data sheet 26 v2.0, 2011-03 figure 14 ssc spike filter filter for data and cs the following conditions apply: ? the data pin has a ?2-of-3? filter ?the cs input has a ?2-of-3? filter that suppresses only positive spikes 3.9.4 ssc data transfer the following transfer byte are possible: ? command byte (to access and change operating modes of the tle5011) ? data bytes (any data transferred in any direction) ? crc byte (cyclic redundancy check) ? slave-active byte (respons e of all selected slaves) figure 15 ssc data transfer (data read example) 3.9.5 ssc command byte the tle5011 is controlled by a command byte. it is sent first at every data transmission. table 15 structure of the command byte name bits description rw [7] read - write 0 = write, 1 = read addr [6..3] address to be read / written 0..15 - register start addres s (address auto increment) nd [2..0] number of data bytes 0..7 - numb er of data bytes to be transferred sck (pad) sck rise sck fall masked, because no fall detected suppressed spike sck fall detected sck rise detected ) ) ) ) sck data command byte data byte(s) ssc- master is driving data ( c) ssc- slave is driving data (sensor) cs data com mand byte data crc slaveactive ssc- slave is driving data (sensor ) ssc-master is dr iving data ( c) lsb 32 1 msb 6 5 4 lsb 32 1 msb 6 5 4
tle5011 specification final data sheet 27 v2.0, 2011-03 register table this section describes the complete address range as well as all registers of the tle5011. it also defines the read/write access rights of the specific registers. table 16 identifies the values with symbols. access to the registers is accomplished via the ssc interface. bit types the types of bits used in the registers are listed here: table 16 address map addr. name bits 765 4 32 10 00 h ctrl1 - - - - ssc_ filt - auto ur 01 h xl x low 02 h xh x high 03 h yl y low 04 h yh y high 05 h fcnt_ stat - stat_ vr gmr_ off update fcnt 06 h fsync_in v filt_ inv fsync 07 h angt - angt_e n angt_y angt_x 08 h - reserved 09 h - reserved 0a h - reserved 0b h - reserved 0c h tst temp_e n adcpy filt_ par filt_ crs filt_ byp tst_ adc tst_ gmr tst_ chan 0d h id dev_id reserved 0e h lock lock 0f h crtl2 vdd_ov vdd_ off gnd_of f vrg_ ov vra_ ov vrd_ ov s_no abbreviation function description l locked locked register. locked registers can be written onl y when the unlock-value is written in the lock register ( 0e h ). this ensures that these bits cannot be modified unintentionally during normal operation. u update update buffer for this bit is present. if an update command is issued and the update-mode bit (ur in ctrl1) is set, the immediate values are stored in this update buffer simultaneously. this enables a snapshot of all necessary system parameters at the same time.
tle5011 specification final data sheet 28 v2.0, 2011-03 s status reset only after readout r read read-only registers w write read and write registers ctrl1 addr: 00 h reset value: 01 h 76543210 reserved reserved reserved reserved ssc_filt reserved auto ur ---w lw l-w lw l field bits type description reserved 7 - reserved, must be set to 0 reserved 6 - reserved, must be set to 0 reserved 5 - reserved, must be set to 0 reserved 4 - reserved, must be set to 0 ssc_filt 3 w l ssc digital spike filt er enable for all ssc lines ( cs , clk and data ) 0: digital ssc spike filters off 1: digital ssc spike filt ers on (modified timing) reserved 2 - reserved, must be set to 0 auto 1 w l automatic update at angle tests 0: no automatic update in angle test mode 1: automatic update-command after t settle , counters fsync and fcnt are reset to 0. then the angle-test (angt_en) is automatically disabled and switches back to normal operation. also, the update bit is toggled ur 0 w l update / run mode 0: run mode (buffer1 values are immediate values) 1: update mode (buffer2 values are stored values) the values in register 01h to 04h represent one by te of two?s complement signed 16 bit integer values. x_l addr: 01 h reset value: 00 h 76543210 x low byte r u x_h addr: 02 h reset value: 00 h 76543210 x high byte r u abbreviation function description
tle5011 specification final data sheet 29 v2.0, 2011-03 y_l addr: 03 h reset value: 00 h 76543210 y low byte r u y_h addr: 04 h reset value: 00 h 76543210 y high byte r u fcnt_stat addr: 05 h reset value: 80 h 76543210 reserved stat_vr gmr_off update fcnt -r sr ur s r u field bits type description reserved 7 - stat_vr 6 rs voltage regulator status this bit is a logical or combin ation of digital, analog, gmr and vdd_ov comparator and gnd_off, and vdd_off comparator outputs. 0: voltage supply ok 1: voltage supply is not ok gmr_off 5 ru adc values are no gmr values (e.g.: temperature measurement is active) this bit indicates whether or not gmr values or any other values are connected to the adcs. this value is read back from the multiplexer control signals. 0: x,y values are gmr values 1: x,y values normally represent temperature measurement or angle test values. in the case of non-functional mux, this bit is set to 1 update 4 ru update toggle bit. this bit toggles after every update (update command or automatic update at angle test) the bit is independent of ur bit in ctrl1 fcnt 3-0 ru frame counter (4-b it unsigned integer value) this counter counts every new x,y value pair coming out of the data path. (approx. 80s) this counter is reset to 0 h after any write to f sync and after every change of the angt_en bit. as t settle time has to elapse for valid x,y data, this counter must be 2 h to indicate valid x,y values. if it overflows, it resets to 3 h to show that values are still valid. note: if fir_byp is activated, this counter counts four times faster!
tle5011 specification final data sheet 30 v2.0, 2011-03 reserved registers (08 h to 0b h ) the values in these registers ar e 8-bit unsigned integer values. the values in addr.8 and addr.9 have to be in reset status. fsync_inv addr: 06 h reset value: 00 h 76543210 filt_inv fsync wu wu field bits type description filt_inv 7 wu filter input inversion (to check the digital data path during operation) 0: filter inputs are not inverted 1: filter inputs are inverted fsync 6-0 wu frame synchronization (7-bit unsigned integer value) the filter update time of approx. 80 s results from the filter decimation. the phase of this decimation can be set and checked by this counter. if fir_byp is activated, this counter overflows at the value 31 d . angt addr: 07 h reset value: 00 h 76543210 reserved angt_en angt_y angt_x -w w w field bits type description reserved 7 - reserved, must be set to 0 angt_en 6 w angle test enable 0: angle test disable command 1: angle test enable command in this case x and y values represen t resistive test values that can be used to simulate angle values angt_y 5-3 w angle test x and y value see : table 18 ?functional angle test? on page 37 angt_x 2-0 w reserved addr: 08 h reset value: ff h 76543210 reserved
tle5011 specification final data sheet 31 v2.0, 2011-03 reserved addr: 09 h - 0b h reset value: 00 h 76543210 reserved tst addr: 0c h reset value: 00 h 76543210 temp_en adcpy filt_par filt_crs fir_byp tst_adc tst_gmr tst_ chan w lw lw lw lw lw lw lw l field bits type description temp_en 7 w l temperature device enable 0: temperature measurement disabled 1: temperature measurement enabled the x value represents the temperature. automatic update mode enabled, if auto=1 adcpy 6 w l y polarity 0: no inversion of y bitstream 1: inversion of y bitstream (rotating direct. changed) filt_par 5 w l filter switched parallel 0: filters in normal mode 1: filters paralle l, input select ed by tst_chan filt_crs 4 w l filter switched across 0: filters in normal mode 1: filters crossed, x and y outputs are exchanged fir_byp 3 w l fir filter bypass 0: no fir bypass 1: fir bypass tst_adc 1) 1) only for test purposes 2 w l adc input switch to tst1and tst2 0: no adc input switch, normal operation 1: adc input switched to tst1 ,2, adc selected by tst_chan 2) 2) if tst_adc and tst_gmr are set to 1 at the same time , tst_gmr is forced to 0. ts t_adc has the higher priority. tst_gmr 1) 1 w l gmr switch to tst1and tst2 0: no gmr switch , normal operation 1: gmr switched to tst1,2 selected by tst_chan 2) tst_chan 0 w l test channel select 0: x channel linked to tst1and tst2 1: y channel linked to tst1and tst2
tle5011 specification final data sheet 32 v2.0, 2011-03 id addr: 0d h reset value: 12 h 76543210 dev_id reserved rr field bits type description dev_id 7-4 r device identifier 001 h : tle5011 production chip reserved 3-0 - lock addr: 0e h reset value: 00 h 76543210 lock w field bits type description lock 7-0 w lock byte 5a h : lock registers locked = 5a h : lock registers unlocked ctrl2 addr: 0f h reset value: 00 h 76543210 vdd_ov vdd_off gnd_off vrg_ov vra_ov vrd_ov s_no r sr sr sr sr sr s w l field bits type description vdd_ov 7 r s v dd overvoltage comparator 0: no v dd overvoltage occurred 1: v dd overvoltage occurred vdd_off 6 r s v dd - off comparator 0: no v dd - off occurred 1: v dd - off occurred gnd_off 5 r s gnd - off comparator 0: no gnd - off occurred 1: gnd - off occurred vrg_ov 4 r s gmr voltage regu lator overvoltage comparator 0: voltage ok 1: vrg overvoltage occurred
tle5011 specification final data sheet 33 v2.0, 2011-03 3.9.6 data communication via ssc data communication via the ssc interface has the following characteristics: ? the data transmission order is ?m ost significant bit (msb) first?. ? data is put on the data line with the rising edge on sck and read with the fa lling edge on sck. ? the ssc interface is byte-aligned. all functi ons are activated after each transmitted byte. ? a ?high? condition on the negated chip select pin (cs ) of the selected tle5011 interrupts the transfer immediately. the crc calculat or is automatically reset. ? every access to the tle5011 wi th the number of data (nd) 1 is performed with address auto-increment. ? after an auto-increment overflow, the addresses begin from 00 h . ? for every data transfer with nd 1, an 8-bit crc byte will be appended by the selected tle5011. no crc byte is sent in a data transfer with nd = 0 (e.g. update command). ? after the crc byte is sent, the bit represented by s_no is pulled low by the selected slave in the slave-active- byte (bits [3..0], low nibble). in this way, broadcast messages also produce individual feedback of every selected slave. this is necessary to differentiate am ong the individual tle5011 slave responses, because the crc byte is written by both tle5011 units in parallel. ? if the crc byte on the bus is the same as the interna lly generated crc of each tle5011, each slave pulls the dedicated bit in the slave-active by te (bits [7..4], high nibble) low. if not, the bit in the high nibble remains 1. ? a write command to address 00 h with nd = 0 will update all values inside the tle5011, and on ly in this case can the transfer proceed. furthermore, this command is added to the crc calculation of the following ssc transfer. ? a command of 0000_0000 is called update command . this command transfers the present imme diate values of each register to the update register. after an update command, the cs line does not need to be set and reset again. ? the transfer ends after the crc and slave-active byte have been sent. the tle5011 always sends logical 1 and all following sent bits from the ssc master are ignored (tle5011 is in idle mode). to enable data transfers again, the chip select pin (cs ) of the tle5011 must be deselected for cs off (see table 13 ) once. ? if the update mode is selected (ctrl register, ur = 1), all accesses are performed to update registers where update registers are present. other registers are accessed directly. vra_ov 3 r s analog voltage regulator overvoltage comparator 0: voltage ok 1: vra overvoltage occurred vrd_ov 2 r s digital voltage re gulator overvoltage comparator 0: voltage ok 1: vrd overvoltage occurred s_no 1-0 w l slave number used in the ssc protocol field bits type description
tle5011 specification final data sheet 34 v2.0, 2011-03 3.9.7 crc generation these are the requirements for crc generation: ? this crc is defined according to the j1850 bus-specification of 15.feb.1994 for class b data communication. ? every new transfer rese ts the crc generation. ? every byte of a transfer will be ta ken into account to generate th e crc [also the sent command(s)]. ? generator polynomial: x8+x4+x3+x2+1, the fast crc generation circuit, is used for crc generation. (see figure 16 ) ? the remainder of the fast crc ci rcuit is initially set to 11111111 b . ? the remainder is bit-inverted before transmission. figure 16 shows the fast crc polynomial. the zero extension for initia l crc calculation is included! figure 16 fast crc polynomial division circuit 3.9.8 slave-active byte generation the position of the 0 in a nibble corr esponds to the given slave number. the slave-active byte (cccc_nnnn) consists of: ? low nibble (nnnn). one 0 is generated always according to the slave number. ? high nibble (cccc). the 0 is only generated, if the readback crc is correct. slave1: s_no = 0 ? bit 0 is pulled low slave-active byte: 1110_1110 slave2: s_no = 1 ? bit 1 is pulled low slave-active byte: 1101_1101 slave3: s_no = 2 ? bit 2 is pulled low slave-active byte: 1011_1011 slace4: s_no = 3 ? bit 3 is pulled low slave-active byte: 0111_0111 example of a communication disturbed by other bus participants: slave1: s_no = 0 ? bit 0 is pulled low, but the high nibble remains as ?1111?. > slave-active byte: 111 1 _1110 x7 x6 x5 x4 x3 x2 x0 xor input serial crc output tx_crc x1 1 1 xor 1 xor 1 xor 1 1 1 1 & parallel remainder
tle5011 specification final data sheet 35 v2.0, 2011-03 example1: crc calculation (update x and y and set adc-test mode) command data crc (init all ?0?) 00000001 00000101 00000000 ----------------------------------- xor 11111111 -------- =11111110.0 . .a xor 10001110.1 . . --------.- . . = 01110000.10 . .b xor 1000111.01 . . -------.-- . . = 0110111.110 . .c xor 100011.101 . . ------.--- . . = 10100.0110 . .d xor 10001.1101 . . -----.---- . . = 00101.101101 . .e xor 100.011101 . . ---.------ . . = 001.11000001. .f xor 1.00011101. . ---.------ . . =.11011100.0 .g xor.10001110.1 . .--------.- . = 1010010.10 .h xor 1000111.01 . -------.- . = 10101.1100 .i xor 10001.1101 . ----.----- . = 100.000100 .j xor 100.011101 . ---.------ . =01100100. remainder 10011011 inverted remainder transmitted sequence: command data crc 00000001 00000101 10011011
tle5011 specification final data sheet 36 v2.0, 2011-03 example2: use of two tle5011 units in a bus mode. table 17 update x,y of two tle5011 units, and read first tle5011 ssc byte no. description master transmitting tle5011 transmitting 1 command 1) 1) both tle5011 are selected (cs 1 =cs 2 =active) during this command byte. 0_0000_000 (update all tle5011) - 2 command 2) 2) cs 2 of the second tle5011 slave is deac tivated after the second command byte. 1_0001_110 (read first tle5011) - 3 data byte 1 to 01 h -xl 4 data byte 2 to 02 h -xh 5 data byte 3 to 03 h -yl 6 data byte 4 to 04 h -yh 7 data byte 5 to 05 h - fcnt_stat 8 data byte 6 to 06 h - fsync_inv 9 crc - calc. crc value 10 slave-active - cccc_nnnn 11 command 3) 3) cs 1 of the first tle5011 slave is deactivated after the third command byte. 1_0001_110 (read second tle5011) - 12 data byte 1 to 01 h -xl 13 data byte 2 to 02 h -xh 14 data byte 3 to 03 h -yl 15 data byte 4 to 04 h -yh 16 data byte 5 to 05 h - fcnt_stat 17 data byte 6 to 06 h - fsync_inv 18 crc - calc. crc value 19 slave-active - cccc_nnnn
tle5011 specification final data sheet 37 v2.0, 2011-03 3.10 test structures two different test signal structures are implemented in the tle5011: ? functional angle test. in this case, well-known signals feed the adcs. ? temperature measurement. this is useful to read out the chip temperature for compensation purposes. 3.10.1 functional angle tests it is possible to feed the adcs wit h appropriate values to simulate a certain magnet position and other gmr effects. the values are generated with resistors on the chip. the following x / y adc values can be programmed: ? 4 points, circle amplitude = 70.7% (0, 90, 180, 270) ? 8 points, circle amplitude = 100.0% (0, 45, 90, 135,180, 225, 270, 315) ? 8 points, circle amplitude = 122.1% (35.3, 54.7, 125.3, 144.7, 215.3, 234.7, 305.3, 324.7) ? 4 points, circle amplitude = 141.4% (45, 135, 225, 315) note: the 100% values typically correspond to 21700 digits and a voltage of ~ 110 mv. table 18 functional angle test register bits x / y values (decimal) min. typ. max. 000 -400 0 400 001 14800 15500 16200 010 20700 21700 22700 011 32767 100 1) 1) not allowed to use. -400 0 400 101 -16200 -15500 -14800 110 -22700 -21700 -20700 111 -32768
tle5011 specification final data sheet 38 v2.0, 2011-03 adc test vectors figure 17 adc test vectors 3.10.2 temperature measurement an internal bandgap voltage can be used to measure the temperature on the chip. this may be used to compensate for temperature-dependent errors. the temperature values is sent out instead of the x value. table 19 temperature measurement parameter symbol limit values unit notes min. typ. max. value at -40c t -40 - - +22000 digits value at 25c t 25 +2550 +5775 +9000 digits value at 150c t 150 -22000 - - digits temperature sensitivity s t - -188.75 - dig / k 1) 1) should be used for temperature compensation of offset errors x y 0% 122.1% 100.0% 70.7% 141.4%
tle5011 specification final data sheet 39 v2.0, 2011-03 3.10.3 functional angle test and temperature measurement timing the functional angle test and the temperature readout are based on the same mechanism. in the normal mode, the output path is linked to the functional angle test or to the temperature measurement unit until the mode is terminated. figure 18 measurement in normal mode in automatic mode, the signal is automatically switch ed back to gmr measurement after the read-out of one value. figure 19 measurement in automatic mode adc&filter val_g4 fcnt[4] 4 val_g5 val_a0 val_a1 1 fsync (reset) update gmr_off val_g1 1 val_g0 useful x[16],y[16] buffer1 val_g3 val_g0 val_g1 val_g2 2 val_a0 t upd t upd t upd t upd < t upd < t upd t upd t upd 0 5 0 2 val_a2 val_a1 val_g4 angt_en or temp_en no gmr signal available val_g4 4 val_g5 val_a0 val_a1 1 val_g1 0 1 val_g0 val_g3 val_g4 val_a1 val_g1 val_g2 2 automatic! val_a0 val_g0 t upd t upd t upd t upd t upd t upd < t upd 0 5 updated fcnt=2 adc&filter fcnt[4] angt_en or temp_en fsync (reset) update gmr_off x[16],y[16] buffer1 no gmr signal available
tle5011 specification final data sheet 40 v2.0, 2011-03 3.11 overvoltage comparators various comparators monitor the voltage in order to ensure error-free operation. the overvoltages must be active for at least t del to set the test comparator bits in the ssc interface registers. this works as digital spike suppression. 3.11.1 internal supply voltage comparators every voltage regulator has an overvoltage comparator to detect a malfunction. if the nominal output voltage of 2.5 v is larger than v ovg , v ova and v ovd , then this overvoltage comparator is activated. it sets the vrx_o v bit. . figure 20 ov comparator 3.11.2 v dd overvoltage detection the overvoltage detection comparator monito rs the external supply voltage at the v dd pin. it activates the stat_vr (see figure 20 ). 3.11.3 gnd-off comparator the gnd-off comparator is used to detect a voltage di fference between the gnd pin and tst1 (which must be soldered to gnd in the app lication). it activates the stat_vr bit. this circuit can detect a disconnection of the supply gnd pin. table 20 test comparators parameter symbol limit values unit notes min. typ. max. overvoltage detection v ovg -2.80-v v ova -2.80-v v ovd -2.80-v v dd overvoltage v ddov -6.5-v gnd - off voltage v gndoff -0.54-v v gndoff = v gnd - v tst1 v dd - off voltage v vddoff - 0.48 - v v vddoff = v clk - v dd or v sck - v dd spike filter delay t del - 10 - s the error condition has to last longer than this value (min. 256 clocks of f dig ) ref - + 10s spike filter xxx_ov v dda gnd gnd v dd v rg v ra v rd
tle5011 specification final data sheet 41 v2.0, 2011-03 . figure 21 gnd-off comparator 3.11.4 v dd -off comparator the v dd -off comparator detects a disconnection of the v dd pin supply voltage. in this case, the tle5011 is supplied by the sck, clk and cs input pins via the esd st ructures. it activates the stat_vr bit. the retriggerable analog monoflop is necessary because of the non-static signal of the clk and sck signals. this comparator is also activated if sp ikes on clk or sck achieve the condition: ( v clk - v dd )> v vddoff or ( v sck - v dd )> v vddoff . figure 22 v dd - off comparator - + 10s spike filter gnd_off v dda gnd tst1 gnd v dd +dv v gndoff 10s spike filter vdd _off v dda gnd v dd clk sck -dv gnd 1s mono flop - + v vddoff
tle5011 package information final data sheet 42 v2.0, 2011-03 4 package information 4.1 package parameters package outline pg-dso-8 figure 23 pg-dso-8 package dimension table 21 package parameters parameter symbol limit values unit notes min. typ. max. thermal resistance r thja - 150 200 k/w junction to air 1) 1) according to jedec jesd51-7 r thjc - - 75 k/w junction to case r thjl - - 85 k/w junction to lead soldering moisture level msl 3 260c lead frame cu plating sn 100% > 7 m
tle5011 package information final data sheet 43 v2.0, 2011-03 figure 24 position of sensing element footprint pg-dso-8 figure 25 footprint pg-dso-8 packing figure 26 tape and reel 0.65 1.31 5.69 1.27 8 6.4 5.2 0.3 0.3 12 2.1 1.75
tle5011 package information final data sheet 44 v2.0, 2011-03 marking processing note: for processing recommendations, please refer to infineon?s notes on processing position marking description 1st line 5011xx see ordering table on page 6 2nd line xxx lot code 3rd line gxxxx g .. green, 4-digit .. date code
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